1. Field of the Invention
The present invention relates generally to chrominance signal processing circuits and video tape recorders (hereinafter, referred to as VTR) having a function of processing a chrominance signal and, more particularly, to an integrated chrominance signal processing circuit for converting a frequency of a chrominance signal in recording and reproducing of a video signal and a VTR comprising such a chrominance signal processing circuit.
2. Description of the Background Art
Conventionally, 2-head helical scanning system has been adopted in a home VTR. In a VTR of such a 2-head helical scanning system, no signal region e.g. a guard band is not provided between tracks in order to achieve high density recording, therefore, in reproducing, a crosstalk occurs from an adjacent track. Crosstalk is removed for example from a chrominance signal among signals recorded on a video tape by utilizing a line correlation.
FIG. 3 is a circuit diagram showing one example of a chrominance signal processing circuit provided in a reproduction system of a video signal in a conventional VTR, which is in effect implemented as an integrated circuit. The chrominance signal processing circuit converts a low-frequency converted and recorded chrominance signal into a high-frequency signal after being reproduced from a video tape, and removes a crosstalk from the high frequency signal. The example shown in FIG. 3 is for reproducing a video signal of NTSC system.
In FIG. 3, a reproduced video signal from a head (not shown) is applied to an input terminal 1. Only a chrominance signal of 629 KHz of the applied video signal passes through a low-pass filter (LPF) 2 to be inputted to a first frequency converting circuit 3. The first frequency converting circuit 3 causes the chrominance signal of 629 KHz to be converted into a chrominance signal of 4.21 MHz.+-.629 KHz. The frequency converted chrominance signal is supplied to a band-pass filter (BPF) 4 through which only a chrominance signal of 3.58 MHz is extracted. The extracted chrominance signal of 3.58 MHz is applied to a comb filter 5 wherein noise components are removed. Then, the output of the comb filter 5 is supplied to an output terminal 6.
The chrominance signal outputted from the comb filter 5 is applied to a burst extracting circuit 7 at the same time. The burst extracting circuit 7 extracts a burst signal from the chrominance signal in response to a burst gate pulse (BGP) supplied from a terminal 8, thereby applying the burst signal to one input of a phase comparator circuit (PC) 9. On the other hand, an oscillating output signal having a center frequency of 3.58 MHz is applied to the other input of the phase comparator circuit 9 from a first oscillation circuit 10, and the phase comparator circuit 9 compares phases of both of the inputted signals. Then, an error output corresponding to the result is smoothed in a low-pass filter 11 and applied to a second voltage controlled oscillator (VCO) 12.
An output of the VCO 12 is applied to a frequency limiting circuit 13, and when an oscillating frequency of the VCO 12 fluctuates, the frequency limiting circuit 13 generates an error signal corresponding to the fluctuation, thereby feeding back the same to the VCO 12. As a result, a frequency of the oscillating output signal of the VCO 12 is prevented from deviating from a predetermined range, so that oscillation of the VCO 12 is stabilized.
A central frequency of the oscillating output of the VCO 12 is set to 320f.sub.H (f.sub.H is a horizontal frequency of 15.734 KHz), and the oscillating output signal is applied to a 1/8 frequency dividing circuit 14, wherein its frequency is frequency-divided into 1/8. The 1/8 frequency dividing circuit generates four frequency-divided signals which are out of phase from each other by 90.degree.. Accordingly, the four signals shifted by 90.degree. and each having a frequency of 40f.sub.H are applied to a four-phase logic circuit 15. The four-phase logic circuit 15 selects any of four inputted signals of 40 f.sub.H to supply the same, and its selection is switched corresponding to a horizontal synchronizing signal supplied from a terminal 16. More specifically, a signal whose phase is advanced (or delayed) by 90.degree. every 1H (H is one horizontal cycle) is selectively supplied to be applied to a second frequency converting circuit 17. An output of the four-phase logic circuit 15 is multiplied by an oscillating output of 3.58 MHz of the first oscillation circuit 10 by the second frequency converting circuit 17 to be applied to a band-pass filter 18. Then, only a signal having a frequency component of a sum (40f.sub.H +3.58 MHz=4.21 MHz) of the multiplication result passes through the band-pass filter 18 to be applied to the first frequency converting circuit 3. As a result, in the first frequency converting circuit 3, a chrominance signal of 629 KHz and the above described signal of 4.21 MHz are multiplied, so that its result is applied to the band-pass filter 4. Then, only a signal of 3.58 MHz which is a frequency component of a difference of the multiplication result passes through the band-pass filter 4 to be applied to the comb filter 5.
The comb filter 5 has a 1H delay line using CCD or a glass delay line, and removes crosstalk by subtracting a chrominance signal advanced by 1H and a chrominance signal delayed by 1H to each other. A signal having a frequency of 2f.sub.SC (f.sub.SC is a chrominance subcarrier frequency of 3.58 MHz) is required to drive such a CCD. In the circuit of FIG. 3, such a 2f.sub.SC signal is obtained by multiplying by double an oscillating output of f.sub.SC of the first oscillation circuit 10. More specifically, the oscillating output of the first oscillation circuit 10 is applied to a multiplying circuit 19 directly and through a 90.degree. phase shift circuit 20. Then, only a signal having a frequency of 2f.sub.SC in multiplication results of the multiplying circuit 19 is extracted by a band-pass filter 21 to be supplied to the comb filter 5. On the other hand, the signal of 2f.sub.SC is also used for a noise removing circuit (not shown) built in a luminance signal processing circuit 22.
As the foregoing, in the chrominance signal processing circuit shown in FIG. 3, a reproduced chrominance signal of 3.58 MHz can be obtained by inversely converting the low-frequency converted and recorded chrominance signal, and a crosstalk is removed from the reproduced chrominance signal.
A VTR comprising the above described chrominance signal processing circuit is disclosed in Japanese Patent Laying Open No. 62-104296.
In the circuit of FIG. 3, the four-phase logic circuit 15 shifts the oscillating output of the VCO 12 by 90.degree. every 1H. Accordingly, in an output signal of the four-phase logic circuit 15, a sideband having offset of f.sub.H /4 to 40f.sub.H occurs every 1H, and a sideband corresponding thereto also occurs in an output of the second frequency converting circuit 17. If Q of the band-pass filter 18 is high as shown in FIG. 4, the above described sideband cannot pass through the filter, thereby requiring more time for a phase change of every 1H, which results in distortion of waveform of the chrominance signal near the burst signal. Accordingly, as the band-pass filter 18, usually the one having a wide pass band as shown in FIG. 5 is used.
A band-pass filter having filter characteristics as shown in FIG. 5 cannot be implemented in a commonly used parallel resonance circuit as shown in FIG. 6 which is formed of a coil and a capacitor, but a structure of the above described band-pass filter becomes complicated such as shown in FIG. 7. Since the band-pass filter shown in FIG. 7 is implemented as an externally provided part of IC as shown, the number of externally provided parts is increased, and two external pins are necessary for every IC. As the foregoing, in the chrominance signal processing circuit as shown in FIG. 3, there were various difficulties in integrating a circuit.
In addition, in the chrominance signal processing circuit in FIG. 3, the multiplying circuit 19, the 90.degree. phase shift circuit 20 and the band-pass filter 21 are required in order to generate a signal of 2f.sub.SC to be supplied to the comb filter 5 and the luminance signal processing circuit 22, so that the number of the elements is increased. Although the band-pass filter 21 can be implemented in a simple structure shown in FIG. 6, it is implemented as being externally attached to IC, which particularly obstructs integration of a circuit.
In order to resolve the above described problems, the chrominance signal processing circuit is proposed in which an output of the second frequency converting circuit is applied to a band-pass filter having high Q and a phase of the signal passes through the band-pass filter is shifted, which is disclosed in "Development of Color Signal Processor for VHS VTR" by N. Yamamoto et al., in the ITEJ Technical Report, Vol. 12, No. 17, pp.1 through pp.6, issued in May, 1988.
FIG. 8 is a block diagram showing main parts of such an improved chrominance signal processing circuit. In FIG. 8, an oscillating output of 320f.sub.H of the VCO 12 is frequency-divided into 1/8 in the 1/8 frequency dividing circuit 14 to be a signal of 40f.sub.H, and applied to the second frequency converting circuit 17. On the other hand, a signal of f.sub.SC from the first oscillation circuit 10 is applied to the second frequency converting circuit 17. An output of f.sub.SC +40f.sub.H is extracted from an output of f.sub.SC +40f.sub.H of the second frequency converting circuit 17 by a band-pass filter 118 having high Q to be applied to a four-phase logic circuit 115. An output of the four-phase logic circuit 115 is supplied to the first frequency converting circuit 3. Since the above described chrominance signal processing circuit is constituted such that a signal of f.sub.SC +40f.sub.H not containing a sideband component passes through the band-pass filter 118 having high Q, the number of parts externally attached to IC and external pins of IC can be reduced.
However, in the circuit shown in FIG. 8, since an input of the four-phase logic circuit 115 is a signal of f.sub.SC +40f.sub.H, a linear circuit comprising a capacitor and a transistor shown in FIG. 9 should be used in order to generate from the signal of f.sub.SC +40f.sub.H four-phase signals out of phase from each other by 90.degree.. Waveforms 1 through 4 of FIG. 10 indicate potentials of the corresponding nodes 1 through 4 in FIG. 9 and constitute outputs of the four-phase logic circuit. The circuit of FIG. 9 performs only a phase shift by 90.degree. but not a frequency-dividing, however, performing a precise phase shift by 90.degree. is difficult due to a capacitor and a transistor as shown, so that a complicated adjustment is necessary to implement a precise phase shift by 90.degree.. In addition, the capacitor C should be provided externally to the IC in order to secure a large capacitance, which is not suitable for integrating the circuit.